This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
The increasing demand of low power in applications, such as, e.g., IOT (Internet of Things), compels a need to operate SoC (System on a Chip) devices at substantially low voltages, while simultaneously ensuring time-correct read and write operations for memory, such as, e.g., SRAM (Static Random Access Memory). Generally, probability of a successful write may fall sharply with reduction in operational voltage. As such, in some cases, a minimum voltage at which SoC devices are operated may be limited (or bounded) by the periphery voltage of the memory (e.g., SRAM). In some cases, periphery voltage may be kept significantly lesser than core voltage to leverage power savings.
Although the inherent write-ability of bitcells may improve due to a higher core voltage, the bitcells may still have substantial design challenges. For instance, the write-ability of a bitcell for a given core voltage (Vddc) may fall sharply as the periphery voltage (Vddp) is reduced, e.g., due to reduced ground bounce. In some cases, WRM (Write Margin) variation with respect to periphery voltage may show that bitcell write ability degrades significantly as periphery voltage falls. In another instance, high split between core voltage (Vddc) and periphery voltage (Vddp) may result in reverse writes on bitlines, which may result in deteriorating the write margin, thereby limiting (or bounding) a minimum voltage at which periphery (and hence complete SOC) may be operated.
FIG. 1 illustrates conventional memory circuitry 100, which may be used as an example for a typical reverse write situation in memory (e.g., SRAM). For instance, a typical reverse write scenario is represented with core voltage Vddc at operation voltage (e.g., 0.8V) and periphery voltage Vddp near threshold operation voltage (e.g., 0.4V). In this scenario, a bitcell 102 may apply its pre-stored data on its complementary bitlines (BL, NBL) and pull bitline BL down to a substantially low level, depending on what polarity is stored in the bitcell versus what is being written through the write driver.
This scenario may produce a typical reverse write failure at the substantially low periphery voltage (e.g., Vddp=0.4V, when Vddc=0.8V). Due to a continuous fight from the bitcell 102, the bitline NBL on the falling side may get struck with a substantially high voltage (e.g., ˜110 mV) before application of negative assist. As such, this substantially high voltage (e.g., ˜110 mV) may be modelled as assist loss. Further, if the negative assist requirement from the bitcell 102 is, e.g., 40 mV at 0.8V core voltage, then an effective settling assist voltage of, e.g., 110 mV+40 mV=150 mV, may be needed. In some cases, the voltage at the other end of the bitline BL, which may be tightly held at ˜0.4V (˜Vddp level), may fall to about ˜57 mV, due to a weaker PMOS M12 of write driver 2 (driven at Vddp), when compared to a series combination of M8, M6, and M2, which are being operated at Vddc level. This may result in a substantially low ground bounce being developed inside the bitcell and may increase an assist requirement further from ˜150 mV to ˜200 mV. Such assist voltage may be against an original bitcell requirement of 40 mV for write-ability. In this case, 200 mV may be difficult to achieve at 0.4V periphery voltage, while managing breakdown constraints on the higher side of the bitline BL voltage. The corresponding area impact will also will be significantly high.
Therefore, this conventional negative bitline assist scheme may not improve the above discussed limitations generally associated with reverse write situations when the Vddc versus Vddp split is high. In some cases, this effect may be worse at ultra-low periphery voltages, such as, e.g., below 0.4V.